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8086 Processor Architecture. The assembly level programming 8086 is based on the memory registers. A Register is the main part of the microprocessors and controllers which are located in the memory that provides a faster way of collecting and storing the data. If we want to manipulate data to a processor or controller by performing multiplication, addition, etc., we cannot do that directly in. EAX: 0x00000000: EBX: 0x00000000: ECX: 0x00000000: EDX: 0x00000000: ESI: 0x00000000: EDI: 0x00000000: EBP: 0x00000000: ESP: 0x00000000: EIP: 0x00000000.

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This tool takes x86 or x64 assembly instructions and converts them to theirbinary representation (machine code). It can also go the other way, takinga hexadecimal string of machine code and transforming it into a human-readablerepresentation of the instructions. It uses GCC and objdump behind the scenes.

You can use this tool to learn how x86 instructions are encoded or to help withshellcode development.

Assemble

Enter your assembly code using Intel syntax below.

Disassemble

Paste any hex string that encodes x86 instructions (e.g. a shellcode) below.Non-hex characters are skipped over, so you don't have to remove the doublequotes or 'x' if you're disassembling a C-style stringliteral!

Starting with the 8086, it has 14 registers. Four of which are actually eight more registers (AX is AH and AL; BX is BH and BL; CX is CH and CL; DX is DH and DL). Each of these registers has a special purpose (BX can be used to index memory, the rest can't; CX is used in some instructions as a count; AX is your accumulator, and DX is ... just there). There are four more special purpose index registers, SI, DI, BP and SP. SI and DI support post-index and post-decrement indexing mode, but you need to set a flag in another register (CF register) to indicate you want the post-increment mode OR the post-decrement mode. SP is the stack register, but you can't use it as an index register (you can starting with the 80386). You can use the BP register as an index register, but it always takes an offset (there is no special mode for a 0 index).

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Then you get to the segment registers. As if things weren't bad enough. There are four, CS to point to code, DS and ES for data, and SS for the stack. You see, the 8086 can address 1MB of memory (20 bits), but it's a 16bit instruction set. So the segment registers contain not the upper 4-bits of the address, but the physical address divided by 16 (or, shifted right four bits). A physical address is formed by SEGMENTx16+OFFSET, giving you 20 bits of address. Most instructions and addressing modes use DS, except if you use BP, which defaults to SS, and the store-post-increment/decrement instructions, which must use ES:DI (DI is incremented---ES doesn't). You can override the segment register for most instructions, but not all (the string instructions, which give you the post-increment/decrement addressing modes are the exception).

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And because of these segment registers, you can have 16 or 32 bit function pointers, 16 or 32 bit data pointers, and 16 or 32 bit stack pointers.

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So what you have is an instruction set that is almost, but not entirely consistently inconsistent. The 80186 gives you a few more instructions. The 80286 adds protected mode (with four levels of protection) with a change of how the segment registers work (in protected mode---they're now indexes into a table of physical addresses for each segment, each of which can only be 64K in size), and the 80386, which extends all the registers to 32 bits in size (except for the segment registers---they're still only 16 bits long), adds new registers only available in the highest protection ring, and paged memory, in addition to keeping the segmented memory, plus allowing all the registers to more general purpose, in addition to keeping the old instruction set.

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I'm really hard pressed to come up with a more convoluted architecture than the x86.